“A key trend is new materials,” said Shay Wolfling, Nova’s chief technology officer.
However, the largest participants are looking for core particles to help provide some degree of mass customization, in which functions can be added as Lego bricks and work as expected.
“We are in a new era,” said William Chen, an ASE researcher.
” Different materials also make it more difficult to predict how these different components work with other components.
I don’t know whether anyone really has a panacea for this solution.
Now we must consider a broader ecosystem.
You have partitions that can be made separately by different companies, and then they talk together,” said Eric Beyne, senior researcher of imec, vice president of R&D and director of 3D system integration project.
So you need to monitor them.
From an economic perspective, I think the number of core particles will not decline.
But the importance of materials and structures is so important now that every atom is important.
“The key is consistent features,” said Mike McIntyre, director of software product management at Onto Innovation.
“In the past, I would stabilize the materials in the laboratory.
You need to develop packaging innovation, as well as various IP interfaces.
We are monitoring the situation.
The challenge now is how to transform the whole chip industry into this decomposition mode.
If any, the number will rise.” The design problem layout is critical to the functionality of these devices and involves many factors, such as use cases, coefficient of thermal expansion, various types of noise, and their performance over time and within a given power budget.
“In view of what happened to Moore’s Law, there has been a lot of investment and interest to make it work.
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These chips may react differently to heat or aging at different rates under different conditions, including the placement of these different cores in the package.
Therefore, although materials such as antimony and bismuth are conducive to communication, I do not want to use these materials to build CPUs, because they will affect the performance of my transistors.
“The current situation of this industry is like a core particle.
Source: The whole industry of Sunrise echoes the above views.
This is happening because everyone has a common goal, that is, heterogeneous integration, stacking cores, and custom solutions.
” Figure 1:2.5D and 3D-IC packages.
The days of developing monolithic chips on the most advanced process nodes are rapidly decreasing.
System level packaging, 3D-IC, 2.5D and fan out are all feasible options.
This is challenging work.” Applications are driving technology solutions.
Once they meet the requirements, I don’t need to measure anything.
” One of the challenges of the material problem is how to integrate chips with different substrates or dielectric films developed and used at different nodes.
So I am building core particles according to the technology most suitable for this core particle.
So you can only do this for non critical time issues, such as L3 cache, rather than L2 cache.
This is Intel’s philosophy, and they are not alone.
“The reason why you choose core particles is to obtain the flexibility of output and performance.
“For example, the current version of SmartCut technology using SOITEC will have combinations such as InPonsilicon or GaN, SiC, SOI, etc.
But this is not just a technology.
This requires time, energy and major adjustments in the company, technology and focus.
to meet the application.” Almost all relevant personnel regard this as a process, not a rapid change, and is full of major obstacles.
This is how it works to create software packages that can be put together to form an entire system.
With each change in the process, if you raise the temperature too much – even if the change in the annealing process is small – you will change the materials The characteristics of the material.
Therefore, we can find the best combination for a specific use case, which may be different from another use case.
The number of questions we are trying to answer is not Win.
So if you want to enter your chip and go deeper into the kernel itself in the hierarchy – such as L1 or L2 cache, you can split the design..
We need equipment, we need design tools, and all of these must work together.
“Chiplet’s ecosystem is actually taking shape,” said Indong Kim, vice president of Samsung Electronics Product Planning.
“This is not only about the flexibility of how to open and close things and put them together, but also about designing different ways to put things together.
I would measure them on some blank wafers to ensure that everything is under control.
You must also be able to find out which are known knowngoodies, and ensure that you have appropriate yield.
“It works, but it does introduce the PHY interface and does not reduce latency.
There may be different densities at the edge of the wafer, which will show different behaviors.
“In the past, we usually considered three parts – users, fabs, and packaging personnel in between.
“The industry is now looking for intelligent integrated solutions,” said Jean Rene ‘Lequepeys, chief technology officer and deputy director of Leti.
Now we have many methods.
In the past, we had only one way forward Method.
Almost everyone who works in the design frontier is looking for some kind of advanced encapsulation using discrete heterogeneous components.
“This is another tool in the toolbox,” said Kim Arnold, chief development officer of BrewerScience.
As the benefits of expansion continue to diminish on each new node, chipmakers are seeking architectures and customizations to improve performance and reduce power consumption.